Nonvolatile memory devices do not lose data stored therein even if power is interrupted. Thus, nonvolatile memory devices are being widely employed in computers, mobile communication terminals, memory cards, and the like.
A flash memory device is commonly used as a nonvolatile memory device. In general, the flash memory device includes memory cells, each of which has a stacked gate structure. The stacked gate structure may include a tunnel oxide layer, a floating gate, an inter-gate dielectric layer, and a control gate electrode, which are sequentially stacked on a channel region.
Recently, new nonvolatile memory devices, such as a resistance random access memory (resistance RAM), have been proposed. A unit cell of the resistance RAM includes a data storage element which has two electrodes and a variable resistive material layer interposed between the two electrodes. The variable resistive material layer, i.e., a data storage material layer, has a reversible variation in resistance according to the polarity and/or magnitude of an electric signal (voltage or current) applied between the electrodes.
A cross-point resistance RAM is disclosed by Hsu et al. in U.S. Patent Publication No. US2004/0108528 entitled “Cross-Point Resistor Memory Array and Method of Fabrication.” According to this disclosure, a colossal magnetoresistive (CMR) material layer or high-temperature superconducting (HTSC) material layer is employed as a data storage material layer. Examples of the CMR or HTSC material layer are a PrCaMnO3 (PCMO) layer and a GdCaBaCO2O5+5 layer. However, in order to form the material layers, at least four kinds of materials may need to be mixed, and the crystalline structure of the resultant material layer may be highly dependent on an underlying layer. Accordingly, the composition ratio of the material layer may be non-uniform across the device. Also, it may be difficult to pattern the PCMO layer or the HTSC material layer using typical photolithography and etching processes, which are widely used in the fabrication of semiconductor devices. Further, according to U.S. Patent Publication No. US2004/0108528, a noble metal layer such as platinum (Pt), iridium (Ir), or ruthenium (Ru) is deposited and polished using a chemical mechanical polishing (CMP) process, thereby forming a lower electrode. However, since the above-described noble metals are chemically very stable, they may be difficult to polish by the CMP process to form the lower electrode.